1. Field of the Invention
The present invention concerns power consumption for computer system memory arrays, and, more particularly, concerns power consumption for such memory arrays with dynamic word line driver circuitry.
2. Related Art
An illustrative computer system memory array 100, as shown in FIG. 1 according to the prior art, has a storage unit 110 that is 64 bits wide and has 128 rows, also known as “lines.” Each line in the memory array has a corresponding word line WL0, etc., through WL127, for writing to the line. (Likewise, there are word lines for reading, not shown.) A word line driver/decoder 120 (also referred to herein simply as a “word line driver” or as a “decoder”) is coupled to the word lines for selecting which line to access. The decoder selects which word line is accessed responsive to receiving seven address bits and a valid bit.
For a memory array 100 having one write port, all 64 bits of the line are accessed in the write operation when a word line is selected. With a row being so wide this is an electrical load that makes it difficult for the decoder 120 to operate fast enough for a high frequency memory system. The row width is only one of the reasons for this timing problem. Also important is the 128 line column width. It takes time to decode 7 address bits into 128 write word lines. Furthermore, these 7 address bits have to be AND'ed with the valid bit. For example to decode word line 0 (0000000), we have: wr0_addr—<0>AND wr0_addr_b<1>AND . . . wr0_addr_b<6>AND wr0_v where “wr0” means write address/valid of port 0, and “_b” means complement. To implement this an 8 input NAND gate is needed.
It is known to use dynamic circuitry for a memory array word line decoder 120, as shown in FIG. 1, because dynamic circuitry tends to be faster than static circuitry. Dynamic circuitry also tends to require less area, and thus permit higher density designs. Dynamic circuitry, of course, operates in cycles timed by a clock signal, CLK. The dynamic circuitry of decoder 120 operates each cycle in a precharge mode and then an evaluate mode as the clock signal, CLK, is deasserted and then asserted. The clock signal, CLK, is buffered to the decoder 120 by a local clock buffer 130, which also receives a valid signal. The buffer 130 permits its output to the decoder to follow the CLK signal input if the valid signal is asserted. Otherwise, if the valid signal is deasserted the buffer 130 deasserts its output, holding the decoder 120 precharged and on standby.
The constant switching of dynamic circuitry consumes power. With ever-increasing circuit densities, power reduction is an Important issue. Therefore, there is a need to reduce power consumption in memory arrays that use dynamic word line drivers.